1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for dynamically adjusting a sampling rate relating to wafer examination for performing a model prediction.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1 illustrates a typical semiconductor wafer 105. The semiconductor wafer 105 typically includes a plurality of individual semiconductor die 103 arranged in a grid 150. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die 103 locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to FIG. 2, a block diagram depiction of a prior art process flow is illustrated. A manufacturing system may determine a sample rate for performing wafer analysis based upon a particular process to be performed on semiconductor wafers 105 (block 210). The manufacturing system may then process the semiconductor wafers 105 (block 220). Upon processing the semiconductor wafers 105 in a batch, the manufacturing system may acquire metrology data based upon the sampling rate (block 230). The sampling rate is used to determine how many and which semiconductor wafers 105 are examined for metrology data acquisition in a lot. Upon an acquisition of metrology data, the system may perform corrections to the processing based upon metrology data analysis (block 240). Upon determining the one or more corrections to be made on the semiconductor wafers 105, the manufacturing system continues processing of the semiconductor wafers 105 (block 250).
Among the problems associated with the current methodology is the fact that data from the sampled semiconductor wafers 105 may not provide an accurate assessment of the state of the metrology data. For example, some processes or a change in a condition in the manufacturing system may call for additional metrology data for performing a more accurate assessment of the state of the metrology data. The predetermined sampling rate may not be adequate to acquire sufficient data to make an accurate assessment of the condition of the processed semiconductor wafers 105. For example, changing conditions, such as changes in the operation of the processing tool and the like, may cause the predetermined sampling rate to be inadequate.
Furthermore, a process model used to perform processes on semiconductor wafers 105 may be modified during the processing phase, such that more data or less data may be required for proper assessment of the processing accuracy. Inadequate metrology data may cause errors in the processing of semiconductor wafers 105. Additionally, insufficient metrology data may result in a lack of process corrections that otherwise may have been made if proper metrology data were available. Conversely, excessive acquisition of metrology data may cause inefficiencies during wafer processing.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.